Design of data acquisition system for coordinate m

Design of data acquisition system for laser scanning vehicle body coordinate measurement

the laser scanning vehicle body coordinate measurement system based on cooperative target is a detection system for non-contact two-dimensional or three-dimensional coordinate measurement by using the four beam laser scanning measurement principle and comprehensively using laser, photoelectric, precision measurement and other technologies. It has the characteristics of non-contact measurement, not easy to damage the surface, simple structure, large measurement distance, small measurement points, strong anti-interference, fast speed, good real-time performance, high precision, and multi-point measurement at the same time. The system is mainly used in the automobile maintenance industry to ensure that the body condition of the accident vehicle after maintenance can meet the technical requirements of PP material widely used in the automobile interior when the original vehicle leaves the factory. In this paper, the data acquisition and processing of the laser scanning coordinate measuring system for vehicle body are introduced in detail

1 measurement system structure

the structural block diagram of the measurement system is shown in Figure 1. The detection system is composed of characteristic target, connector, motor scanning device, laser and its driving circuit, optical path turning system, Hall sensor, photoelectric conversion and signal preprocessing module, data acquisition and AVR processing and upper computer. Each motor scanning device is composed of a motor and its driving circuit, a reflector, a reflector fixing tray and a small magnet installed on the side of the reflector fixing plate. During operation, the motor drives the plane mirror to rotate. When the scanning laser beam is reflected on the feature target through the rotating plane mirror, because the feature target is pasted with the original regression reflection film, the projected beam returns according to the original light path after being reflected by the reflection film, and the laser beam is reflected by the target and then reflected into the laser turning light path through the plane mirror; After being reflected by two parallel 45 ° angle plane mirrors, the optical signal enters the data acquisition system through photoelectric conversion and preprocessing. Together with the motor rotation synchronous pulse signal generated by the hall sensor, the data acquisition circuit is controlled. After data processing, the preliminary three-dimensional coordinates of the measurement points in the sensor system are obtained, and then sent to the upper computer. The computer calculates the data sent and converts the coordinates to obtain the three-dimensional coordinate measurement results of the car body, and displays or prints them out

2 CPLD signal logic processing

data acquisition and processing circuit includes logic control circuit, buffer circuit, MCU interface circuit, etc. Their relationship structure is shown in Figure 2. The logic control circuit collects the signals of each sensor, and then transmits the signals to the single chip microcomputer after buffering by four buffers; The single chip microcomputer combines software to realize the target recognition and three-dimensional coordinate calculation, connects with the upper computer through serial communication, receives the command of the upper computer, and sends the processed data to the upper computer for printing and display. There are 6 channels of sensor signals in total, including 4 channels of photoelectric signals collected by photoelectric module and 2 channels of Hall signals. CPLD is selected for logic control circuit, FIFO chip is selected for buffer, and ATmega128 AVR single chip microcomputer is selected for single chip microcomputer

2.1 pin digital pulse signal preprocessing

first, take the output waveform of Hall sensor as the rough positioning (waveform 1), extract the sampling period positioning waveform from the digital pulse signal output by pin (waveform 2), then locate the data sampling period based on this positioning waveform, and count and fill the digital pulse signal in the whole data sampling period. The falling edge of the positioning pulse (waveform 3) in the sampling period is located by the falling edge of the positioning pulse of the pin output signal, and its rising edge is located by the rising edge of the hall sensor output pulse. The extracted sampling period positioning waveform is shown in waveform 3 in Figure 3

2.2 sampling data cycle generation circuit

due to the continuous rotation of the scanner, in order to ensure that AVR obtains correct scanning data, the sampling data should be within a complete cycle, so the integrity of the sampling cycle must be strictly controlled. Therefore, a sampling period generation circuit controlled by AVR output signal is designed. This circuit takes the sampling period positioning pulse and AVR control signal as the input, and the sampling period signal and the sampling period end signal as the output. At present, the speed regulation system adopting the high-precision converter technology of semiconductor integrated circuit is mature. The waveform after simulation in tusii9.0 is shown in Figure 4. In the figure, TB is the positioning pulse input of sampling period, clear is the control enable signal of AVR output, tout1 is the generated sampling cycle signal, and flag is the end signal of sampling period

2.3 direct control of CPLD on FIFO chip

the main function of CPLD is to count and fill the digital pulse signal, and write the data into the FIFO chip under the control of the control signal enabling. Therefore, the function module of direct control of FIFO is designed in CPLD, including clearing and writing when the price index of FIFO fell to 83.1 points at the end of 2014

2.3.1 FIFO data emptying

when the FIFO is full or AVR starts the data acquisition cycle, the data in the FIFO must be cleared first to prevent FIFO overflow from causing data loss or collecting wrong data. Aiming at the FIFO reset sequence, a reset circuit module controlled by AVR is designed. When executing the clear FIFO command, first write the clear signal Mr level pull down command to CPLD, and the command word is 0xf0; Then write the reset signal Mr level pull-up command to CPLD, and the command word is 0x0f (any non 0xf0 can be used). Since the clock pulse of AVR MCU is 8 MHz, this process must be able to meet the duration requirements of the reset pulse, and the FIFO will be cleared

2.3.2 single channel FIFO data is written into

the frequency of the signal received by the photodiode is relatively high after pre amplification and shaping. Because the system has a total of four channels of signals, AVR has no time to directly read the count value of each jump edge, so it is temporarily cached through FIFO. After the sampling cycle, AVR reads the count value from FIFO. To write the count value into FIFO, there must be a correct write signal. Cy7c433 has requirements for the timing of the read-write signal. The pulse width of the write signal TPW ≥ 15 ns, the data establishment time TSD ≥ 8 ns, and the data holding time thd has no minimum requirements. Accordingly, this paper designs the FIFO data write signal generation circuit shown in Figure 5, which is essentially a jump edge extraction circuit. The input digital pulse signal first delays three clock cycles through three triggers, and then XOR the original signal, so that a low-level pulse with three clock pulse widths can be generated when each jump edge of the signal arrives. When the CPLD clock is selected as 40 MHz, the pulse width of this low-level pulse is 75 ns, which is enough to meet the requirements of FIFO for writing signals

after this low-level write signal is generated, the clock synchronization is also carried out through a level-1 trigger to avoid the problems of competition and adventure that often occur in CPLD design. At the same time, its rising edge is synchronized with the falling edge of the clock pulse, which just meets the requirements of data establishment time in FIFO write timing

2.3.3 4-channel FIFO data processing

there are 4 laser scanning sensors in the whole system, that is, 4-channel signals will be generated, and each signal will generate an independent FIFO write signal, so a total of 4-channel write signals will be generated. When two or more of the four write signals arrive at the same time, the data written into FIFO will produce (1) the calibration and zeroing of the extensometer: the measurement standard length is disordered, resulting in data writing errors or data loss. Therefore, a multi-channel write signal processing circuit is designed. When a write signal is generated in only one channel of signal, a corresponding write signal pulse is generated in the write signal processing circuit; When a write signal is generated in two or more signals, only one corresponding write signal pulse is generated. To avoid data loss, add a 4-bit data source flag bit to the data. When multiple signals arrive at the same time, it corresponds to the flag position "1" generated by the write signal

3 AVR data acquisition

3.1 FIFO address decoding circuit

cy7c433 chip has a data width of 9 bits, so four FIFO chips are used in this system for expansion. The data bus bit width of AVR is 8 bits. In order to reduce the complexity of peripheral circuits, each FIFO chip uses only 8 bits, and the data is read from the high 8 bits to the low 8 bits. Therefore, a total of 4 read signals are required to read one data completely into AVR. The data is read by configuring each FIFO chip with a unique data address, and the data is read by address. Therefore, this paper designs the corresponding FIFO read signal address decoding circuit, and the output signal controls the read signal enable end of FIFO chip. First, the address signal is decoded by a decoder. After the decoding result is synchronized with the write signal, the read enable signals of four FIFO chips are output

3.2 data acquisition program flow chart

based on all the previous analysis and instructions, the C language program of AVR + CPLD + FIFO signal is written. The program includes many sub items, such as FIFO zeroing, acquisition cycle start and stop control, FIFO status judgment, data source analysis, data validity judgment, etc. Finally, accurate and effective data of a scanning cycle are collected for subsequent circuit processing. The test shows that the program achieves the expected purpose